The present invention relates generally to random-access memories of the type fabricated on a monolithic semiconductor chip employing insulated-gate field-effect transistors (IGFETs) and, more particularly, to a memory cell of the cross-coupled transistor type.
As is well known, a digital random access memory comprises a multiplicity of individual storage cells configured into a large array on an integrated circuit chip and suitably addressed, for example, by word and data bit lines. Each individual cell is capable, during a writing operation, of being set by an external signal into either one of two distinct states. So long as power supply voltage continues, the cell remains in the set state indefinitely, or until it is changed to the other state by a subsequent writing operation. The state of the cell can be sensed during a reading operation to retrieve stored data, preferably in a non-destructive manner, i.e., which does not change the state of the memory cell.
In the design of large memory arrays, important considerations are cell size (which influences the number of individual cells which can be fabricated on a single chip), power dissipation, and the speed at which information can be written into and read from the cell. In general, to achieve a small cell size, it is desirable to reduce to a minimum the number of transistors required per cell. Another consideration is that, in some memory cell types, a design compromise must be made between speed and power dissipation.
One general type of prior art static memory cell particularly pertinent in the context of the present invention is a four-transistor cell comprising two pairs of insulated-gate field-effect transistors (IGFETs), all four of the same channel conductivity type. Typically, four enhancement-mode N-channel IGFETs are employed. One pair of transistors in each cell are latch transistors, cross-coupled in a bistable latch configuration, and are connected for selectively switching ON and OFF a pair of paths to ground from a corresponding pair of complementary data input/output nodes. To accomplish this, the latch transistor drain terminals are connected to the data nodes, and the latch transistor source terminals are connected to ground. The other pair of transistors in each cell are gating transistors, and are selectively enabled, both at the same time, to respectively connect the two data nodes to external DATA and DATA lines for both writing data into and reading data from the cell. Cells of this type also include a pair of load resistors connected from a voltage supply line, e.g. +V.sub.DD, to the data nodes. These resistors may comprise ordinary resistors, or may be implemented in various other ways. In many particular designs, it is convenient to fabricate the load resistors in the form of depletion-mode field-effect transistors with the gate of each depletion mode transistor coupled back to the source of the same transistor.
One example of such a prior art memory cell is described hereinbelow in greater detail with reference to FIG. 1. Further, examples of this general type of static memory cell are disclosed in the following U.S. patents: Donnelly U.S. Pat. No. 3,967,252; McKenny et al U.S. Pat. No. 4,251,876; and Nokubo U.S. Pat. No. 4,335,449.
For reasons explained in greater detail hereinbelow with reference to FIG. 1, in prior art static memory cells of this type the load resistors serve two distinct functions: (1) completing the charging of the data nodes up to the +V.sub.DD potential when a logic high (binary "1") is being written into a particular one of the data nodes; and (2) maintaining static memory by providing a current path from +V.sub.DD potential to the pair of cross-coupled latch transistors.
The reason that the load resistors are required to serve the first function identified above is due to a threshold voltage (V.sub.T) offset between the gate and source of the gating transistors when operated in the source follower mode, as discussed in greater detail hereinafter with reference to FIG. 1. However, it may briefly be stated here that, during the operation of writing a logic high into either of the data nodes, the corresponding gating transistor ceases conducting before the particular data node (or, more precisely, the parasitic capacitance associated with the data node) is fully charged to +V.sub.DD potential. To complete the charging, current must flow through the corresponding load resistor.
In view of this first-identified function served by the load resistors in prior art cells, a design compromise must be made between speed and power. In particular, if the value of the load resistance is lowered for greater speed, then a higher power dissipation results.